1. Field of the Invention
Embodiments of the present invention relate to semiconductor testing.
2. Description of the Related Art
Testing is an important step in the production of semiconductor devices for use. Typically, partially or fully completed semiconductor devices may be tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. A test system controller may be coupled to the probe card assembly to send and receive test signals to and from the DUTs over a set of test channels. A test system controller with increased test channels can be a significant cost factor for a test system. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel (sometimes referred to as multi-site testing).
One technique to accommodate testing of components on a wafer with a limited number of test channels is to fan out a signal from a test system controller in the probe card assembly to multiple transmission lines. That is, a test signal normally provided to a single DUT can be fanned out to multiple DUTs in the probe card assembly. This technique can enable testing of an increased number of DUTs during a single touchdown for a fixed number of test system channels.
During testing, some test channels provide inputs to input pins of the DUTs, others test channels monitor for outputs from output pins of the DUTs, and still others provide inputs to and monitor for outputs from input/output (IO) pins of the DUTs. In addition, some channels are used to provide expected result data (expected outputs) used to verify outputs of the DUTs. For a functional DUT, the outputs match the expected outputs. If any output from a DUT does not match its expected output, an indication of a failure for that DUT can be generated. Utilizing test channels to pass expected result data, however, reduces the number of test channels available to pass input/output signals to/from the DUTs. A limit on the number of input/output signals used for testing can affect the number and types of DUTs capable of being tested by the system, can increase test time, and can increase test cost.
Accordingly, there exists a need in the art for a method and apparatus for testing semiconductor devices that attempts to overcome at least some of the aforementioned deficiencies.